1 V, 1.9 GHz CMOS Mixers for Wireless Applications

Abstract

This thesis deals with the design and implementation of 1 V 1.9 GHz mixers using CMOS technology for CDMA applications. The use of CMOS allows the implementation of the mixers on the same chip with the rest of the analog and digital circuits economically while achieving high performance. The mixers topologies explored are a dual-gate mixer and a back-gate mixer. The dual-gate mixer is designed in a 0.5 um SOI process and the back-gate mixer is designed in a 0.25 um standard bulk CMOS process. Equations describing the nonlinear behavior of the CMOS dual-gate mixer are derived. The analysis yields guidelines for improving third-order intermodulation distortion of the mixer. The dual-gate mixer exhibits 1.8 dB conversion gain, -0.8 dBm IIP3 and 9.8 dB noise figure at 1.9 GHz while operating from a 1 V supply with a power consumption of 3 mW and a die area of 1.44 mm2. The back-gate mixer utilizes the inherent lateral bipolar transistor in CMOS. Device simulations were performed to analyze the behavior of the lateral bipolar transistor and extract a model for it. The characteristic of the transistor were verified through measurements. The mixer circuit only draws 1.3 mW from a 1 V supply. The measurement shows a conversion gain of 6.5 dB an IIP3 of -3.5 dBm and a noise figure of 9.7 dB at 1.9 GHz. The chip area is 1.4 mm2.