A 1-V, CMOS on SOI, 1.9-GHz CDMA Low Noise Amplifier

Abstract

This thesis deals with the design and implementation of a 1V, 1.9GHZ low noise amplifier (LNA) using a 0.5[mu]m CMOS on SOI technology with 3 levels of metal. The amplifier is optimized for CDMA applications operating in the 1.93-1.99GHz band. The inductive degeneration topology used in the LNA implementation provides low noise and low power dissipation. The use of CMOS on SOI technology may lead to an optimum single chip implementation of both the analog and digital building blocks of a 1.9GHz transceiver operating from a 1V supply. Such an implementation offers reduced cost and improved reliability. The LNA consists of two amplifying stages with on-chip inductors and capacitors. At 1.96GHz, the amplifier has a 1.9dB noise figure, a 14dB gain and a 3dBm IIP3. It also exhibits 17.4dB input and 28.3dB output return losses respectively in a 50[Omega] system without external matching networks. The circuit draws 10.6mW from a 1V supply and the chip area is 1.1 x 2.4 mm2.