A 10 bit, 50MS/s, Low-Power Pipelined A/D Converter for Cable Modem Applications

Abstract

Cable modems have been recently developed for high speed, bidirectional communication over the broadband hybrid fiber-coaxial network. Such modems use mixed-mode circuits to achieve high performance interactive multimedia communications. The digital back-end circuits in the cable modem are implemented in a submicron CMOS process for low power dissipation and high speed of operation. To realize low cost and single chip modems, the analog front-end circuits must be implemented together with the digital circuits on the same chip. A crucial block in the cable modem is the high performance A/D converter which operates in the in-band downstream receiver and links the analog front-end to the digital back-end circuitry. This thesis deals with the design of a pipelined A/D converter realized using a one bit per stage pipelined architecture for use in cable modems. The A/D converter includes the input track-and-hold circuit, clock timing generator, digital synchronization block and the pipelined stages. The pipelined A/D converter is implemented in a 0.25-[mu]m, 2.5-3.3V CMOS process, with single layer of polysilicon and 5 levels of metallization and uses an area of 3.2mm2. The prototype exhibits a 10 bits resolution at 50MSample/s and 57dB SNDR while dissipating 65mW from a 2.5V supply voltage. The DNL and the INL are -0.5LSB and 0.95LSB respectively and the area of the core excluding pads is 1.2mm2. Compared to the best previous design with the same resolution and sampling speed, this design achieves the same dynamic range at lower supply voltage, lower power dissipation and with a smaller core area.