Capacity Considerations for Data Storage in Memristor Arrays

Abstract

Memristor arrays are a promising memory technology that store information in a crossbar array of two-terminal devices that can be programmed to patterns of high or low resistance. While extremely compact, this technology suffers from the ``sneak-path'' problem: certain information patterns cannot be recovered, as multiple low resistances in parallel make a high resistance seem low. In this thesis we review the current state of memristor technology, including proposed solutions to the sneak-path issue. We extend this discussion by proposing some variations on existing encoding schemes involving one-hot encoding that improve reliability and ease of access, taking into account the scaling of peripheral hardware. We also extend the scope of the discussion by deriving the information capacity of models of multi-layer memristor devices, which is higher than that of the same number of single-layer devices stacked.