Low-power Multi-Gb/s Wireline Communication

Abstract

This thesis discusses low-power wireline receivers with particular focus on clocking circuitry and architectures. These clocking solutions can be used for a 1-D partial response channel as well as for a conventional DC coupled channel. The receiver front end for a 1-D channel requires more consideration to recover an NRZ signal from the received narrow pulses. Two possible solutions are presented. First, a full-rate detection technique is presented, where the speed is limited by the settling time of a latch circuit which has to be less than 1 UI. Second, a novel demuxing technique is introduced. It is demonstrated through theory, simulation and measurement results that the half-rate architecture can improve maximum achievable speed by a factor of 1.6. The distribution and alignment of high-frequency clocks across a wide bus of links is a signi¯cant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a bu®er into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional bu®ering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 um digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. Injection locked oscillators (ILOs) are an attractive clocking tool for low-power area- e±cient wireline receivers. In this work, we explored their use as a clock deskew element, a clock recovery unit and a programmable jitter lter. A study of both LC and ring ILOs indicates signi¯cant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting di®erent phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. First, an ILO based half-rate clock recovery technique is presented, which can be used for AC coupled links where low frequency signal components are attenuated by the channel. The nonlinear path comprises a hysteresis latch that recovers the missing low frequency content and a linear path that boosts the high frequency component by taking advantage of the high pass channel response. By optimally combining them, the front-end recovers NRZ signals up to 13 Gb/s burning only 26 mW in 90 nm CMOS. A simple theory and simulation technique for ILO-based receivers is discussed. The clock recovery technique is veried with experimental results at 5-10 Gb/s in 90 nm CMOS consuming 70 mW and acquiring lock within 1.5 ns. Second, a clock forwarded 65nm CMOS receiver uses two ILOs to frequency- multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Di®erent data rates and latency mismatch between the clock and data paths are ac- commodated by a jitter tracking bandwidth that is controllable up to 300MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200MHz.