Master's Theses (2009 - )

Permanent URI for this collectionhttps://hdl.handle.net/1807/9947

The School of Graduate Studies (SGS) requires doctoral and masters graduands to submit a thesis written as a required element of their degree program in electronic format.

To submit your thesis, follow these instructions:

  1. Online thesis submission system (SGS)
  2. Thesis preparation and submission instructions (SGS)
  3. Thesis submission and publishing guide (Library)

SGS intends to house all available digitized Doctoral and Masters theses by U of T graduate students on this site. The current collection is but a small sample of that scholarly work.

SGS thesis submission instructions

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Browsing Master's Theses (2009 - ) by Author "Abbas, Mustafa Saied"

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    System Level Communication Challenges of Large FPGAs
    (2019-11) Abbas, Mustafa Saied; Betz, Vaughn; Electrical and Computer Engineering
    As FPGA capacity and the complexity of the designs implemented on them have grown, so too have system-level communication challenges. At the design level the typical latency of long distance interconnect grows making them the limiting factor in reaching timing for a design. We explore the use of latency-insensitive design (LID) as a solution. Our best approach gained 2x area efficiency and 18\% less critical path delay over traditional LID, and come at a minimal speed overhead of 3\% compared to a latency-sensitive design. At the architecture level the number of clocks has grown. It is challenging to supply global clocks to all modules efficiently. Therefore, the clock architecture must be flexible to allow for smaller and more power efficient networks to be built. We present a flexible clock modeling format, built into open source CAD tool VPR, to allow clock impacts and architecture options to be explored.